R8C2H datasheet(93/367 Pages) RENESAS

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R8C/2H Group, R8C/2J Group

8. I/O Ports

Rev.1.00

Mar 28, 2008

Page 73 of 341

REJ09B0388-0100

8.1

Functions of I/O Ports

The PDi_j (j = 0 to 7) bit in the PDi (i = 1, 3, 4, 6) register controls I/O of the following: Ports P1, P3_3, P3_7,

P4_3, P4_5, P6_3 to P6_5 in the R8C/2H Group and ports P1, P3_3, P3_7, P4_5, and P6_5 in the R8C/2J Group.

The Pi register consists of a port latch to hold output data and a circuit to read pin states.

Figures 8.1 to 8.3 show the Configurations of I/O Ports. Table 8.3 lists the Functions of I/O Ports. Also, Figure 8.5

shows the PDi (i = 1, 3, 4, or 6) Register (R8C/2H Group). Figure 8.6 shows the Pi (i = 1, 3, 4, or 6) Register (R8C/

2H Group), Figure 8.7 shows the PDi (i = 1, 3, 4, or 6) Register (R8C/2J Group), Figure 8.8 shows the Pi (i = 1, 3,

4, or 6) Register (R8C/2J Group), Figure 8.9 shows Registers PINSR2 and PINSR4, Figure 8.10 shows the PMR

i = 1, 3, 4, 6, j = 0 to 7

NOTE:

1. In the R8C/2H Group, nothing is assigned to bits PD4_0 to PD4_2, PD4_6, PD4_7, PD6_1, PD6_2,

and PD6_7. Bits PD3_0 to PD3_2, PD3_4 to PD3_6, PD6_0, and PD6_6 are reserved.

In the R8C/2J Group, nothing is assigned to bits PD4_0 to PD4_2, PD4_6, PD4_7, PD6_1, PD6_2,

and PD6_7. Bits PD3_0 to PD3_2, PD3_4 to PD3_6, PD4_3, PD4_4, PD6_0, PD6_3, PD6_4, and

PD6_6 are reserved.

8.2

Effect on Peripheral Functions

I/O ports function as I/O ports for peripheral functions (refer to Table 1.5 Pin Name Information by Pin Number

of R8C/2H Group and Table 1.6 Pin Name Information by Pin Number of R8C/2J Group).

Table 8.4 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 1, 3, 4, 6, j = 0

to 7). Refer to the description of each function for information on how to set peripheral functions.

NOTE:

1. In the R8C/2H Group, nothing is assigned to bits PD4_0 to PD4_2, PD4_6, PD4_7, PD6_1, PD6_2,

and PD6_7. Bits PD3_0 to PD3_2, PD3_4 to PD3_6, PD6_0, and PD6_6 are reserved.

In the R8C/2J Group, nothing is assigned to bits PD4_0 to PD4_2, PD4_6, PD4_7, PD6_1, PD6_2,

and PD6_7. Bits PD3_0 to PD3_2, PD3_4 to PD3_6, PD4_3, PD4_4, PD6_0, PD6_3, PD6_4, and

PD6_6 are reserved.

8.3

Pins Other than Programmable I/O Ports

Figure 8.4 shows the Configuration of I/O Pins.

Table 8.3

Functions of I/O Ports

Operation When

Accessing

Pi Register

Value of PDi_j Bit in PDi Register(1)

When PDi_j Bit is Set to 0 (Input Mode)

When PDi_j Bit is Set to 1 (Output Mode)

Reading

Read pin input level

Read the port latch

Writing

Write to the port latch

Write to the port latch. The value written to

the port latch is output from the pin.

Table 8.4

Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 1, 3, 4, 6, j = 0 to 7)

I/O of Peripheral Functions

PDi_j Bit Settings for Shared Pin Functions(1)

Input

Set this bit to 0 (input mode).

Output

This bit can be set to either 0 or 1 (output regardless of the port setting)

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