R8C2K datasheet(365/471 Pages) RENESAS

365 / 471 page

R8C/2K Group, R8C/2L Group

19. A/D Converter

Rev.1.10

Dec 21, 2007

Page 348 of 450

REJ09B0406-0110

19. A/D Converter

The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling

amplifier. The analog input shares pins P0_0 to P0_3, P0_5, and P1_0 to P1_3. Therefore, when using these pins,

ensure that the corresponding port direction bits are set to 0 (input mode).

When not using the A/D converter, set the VCUT bit in the ADCON1 register to 0 (Vref unconnected) so that no

current will flow from the VREF pin into the resistor ladder. This helps to reduce the power consumption of the chip.

The result of A/D conversion is stored in the AD register.

Table 19.1 lists the Performance of A/D converter. Figure 19.1 shows a Block Diagram of A/D Converter.

Figures 19.2 and 19.3 show the A/D converter-related registers.

NOTES:

1. The analog input voltage does not depend on use of a sample and hold function.

When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh

in 10-bit mode and FFh in 8-bit mode.

2. When 2.7 V

≤ AVCC ≤ 5.5 V, the frequency of φAD must be 10 MHz or below.

Without a sample and hold function, the

φAD frequency should be 250 kHz or above.

With a sample and hold function, the

φAD frequency should be 1 MHz or above.

3. In repeat mode, only 8-bit mode can be used.

Table 19.1

Performance of A/D converter

Item

Performance

A/D conversion method

Successive approximation (with capacitive coupling amplifier)

Analog input voltage(1)

0 V to AVCC

Operating clock

φAD(2)

4.2 V

≤ AVCC ≤ 5.5 V f1, f2, f4, fOCO-F

2.7 V

≤ AVCC < 4.2 V f2, f4, fOCO-F

Resolution

8 bits or 10 bits selectable

Absolute accuracy

AVCC = Vref = 5 V,

φAD = 10 MHz

• 8-bit resolution

±2 LSB

• 10-bit resolution ±3 LSB

AVCC = Vref = 3.3 V,

φAD = 10 MHz

• 8-bit resolution

±2 LSB

• 10-bit resolution ±5 LSB

Operating mode

One-shot and repeat(3)

Analog input pin

9 pins (AN2, AN4 to AN11)

A/D conversion start condition

• Software trigger

Set the ADST bit in the ADCON0 register to 1 (A/D conversion starts)

•Capture

Timer RD interrupt request is generated while the ADST bit is set to 1

Conversion rate per pin

• Without sample and hold function

8-bit resolution: 49

φAD cycles, 10-bit resolution: 59φAD cycles

• With sample and hold function

8-bit resolution: 28

φAD cycles, 10-bit resolution: 33φAD cycles

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