R8C2K datasheet(368/471 Pages) RENESAS

368 / 471 page

R8C/2K Group, R8C/2L Group

19. A/D Converter

Rev.1.10

Dec 21, 2007

Page 351 of 450

REJ09B0406-0110

Figure 19.3

Registers ADCON1, ADCON2, and AD

A/D Control Register 1

(1)

Symbol

Address

After Reset

ADCON1

00D7h

00h

Bit Symbol

Bit Name

Function

NOTES:

3. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting

A/D conversion.

b3 b2

VCUT

b1 b0

Refer to the description of the CKS0 bit in the

ADCON0 register function.

b7 b6 b5 b4

—

(b2-b0)

If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined.

CKS1

—

(b6-b7)

Reserved bits

VREF connect bit(3)

0 : VREF not connected

1 : VREF connected

Set the BITS bit to 0 (8-bit mode) in repeat mode.

Reserved bits

Set to 0.

8/10-bit mode select bit(2)

0 : 8-bit mode

1 : 10-bit mode

Set to 0.

Frequency select bit 1

BITS

A/D Control Register 2

(1)

Symbol

Address

After Reset

ADCON2

00D4h

00h

Bit Symbol

Bit Name

Function

NOTE:

0 : Without sample and hold

1 : With sample and hold

If the ADCON2 register is rew ritten during A/D conversion, the conversion result is undefined.

SMP

A/D conversion method select bit

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

—

(b7-b4)

—

(b3-b1)

Reserved bits

Set to 0.

b7 b6 b5 b4

b3 b2 b1 b0

A/D Register

Symbol

Address

After Reset

00C1h-00C0h

Undefined

Function

When BITS bit in ADCON1 register is

set to 1 (10-bit mode).

When BITS bit in ADCON1 register is

set to 0 (8-bit mode).

8 low -order bits in A/D conversion result

A/D conversion result

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

—

2 high-order bits in A/D conversion result

When read, the content is undefined.

(b8)

(b15)

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