R8C2K datasheet(388/471 Pages) RENESAS

388 / 471 page

R8C/2K Group, R8C/2L Group

20. Flash Memory

Rev.1.10

Dec 21, 2007

Page 371 of 450

REJ09B0406-0110

20.4.1.3

FMR4 Register (FMR4)

Figure 20.6 shows the FMR4 Register.

Figure 20.6

FMR4 Register

Flash Memory Control Register 4

Symbol

Address

After Reset

FMR4

01B3h

01000000b

Bit Symbol

Bit Name

Function

NOTES:

5. Set the FMR01 bit to 0 (CPU rew rite mode disabled) in low -current-consumption read mode.

To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit

to 0 and setting it to 1.

This bit is enabled w hen the FMR40 bit is set to 1 (enabled) and it can be w ritten to during the period betw een

issuing an erase command and completing the erase. (This bit is set to 0 during periods other than the above.)

In EW0 mode, it can be set to 0 or 1 by a program.

In EW1 mode, it is automatically set to 1 if a maskable interrupt is generated during an erase

operation w hile the FMR40 bit is set to 1. Do not set this bit to 1 by a program (0 can be w ritten).

b3 b2 b1 b0

FMR41

—

(b5)

FMR40

FMR42

b7 b6 b5 b4

Erase-suspend function

enable bit(1)

0 : Reading disabled

1 : Reading enabled

0 : Disabled

1 : Enabled

Erase-suspend request bit(2)

0 : Erasure restarts

1 : Erase-suspend request

Set to 0.

FMR46

Program-suspend request bit(3) 0 : Programming restarts

1 : Program-suspend request

FMR43

Erase command flag

0 : Erase not executed

1 : Erase execution in progress

FMR44

Reserved bit

In high-speed clock mode and high-speed on-chip oscillator mode, set the FMR47 bit to 0 (disabled).

Program command flag

0 : Program not executed

1 : Program execution in progress

The FMR42 bit is enabled only w hen the FMR40 bit is set to 1 (enabled) and programming to the FMR42 bit is enabled

until auto-programming ends after a program command is generated. (This bit is set to 0 during periods other than the

above.)

In EW0 mode, 0 or 1 can be programmed to the FMR42 bit by a program.

In EW1 mode, the FMR42 bit is automatically set to 1 by generating a maskable interrupt during auto-programming

w hen the FMR40 bit is set to 1. 1 cannot be w ritten to the FMR42 bit by a program.

FMR47

Read status flag

Low -current-consumption

read mode enable bit (1, 4, 5)

0 : Disabled

1 : Enabled

R8C2K Datasheet(PDF) 388 Page - Renesas Technology Corp

R8C2K Datasheet(HTML) 388 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL