R8C2K datasheet(390/471 Pages) RENESAS

390 / 471 page

R8C/2K Group, R8C/2L Group

20. Flash Memory

Rev.1.10

Dec 21, 2007

Page 373 of 450

REJ09B0406-0110

20.4.2

Status Check Procedure

When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the occurrence of an

error. Therefore, checking these status bits (full status check) can be used to determine the execution result.

Figure 20.7 shows the Full Status Check and Handling Procedure for Individual Errors.

Figure 20.7

Full Status Check and Handling Procedure for Individual Errors

NOTE:

1. To rewrite to the address where the program error occurs, check if the full

status check is complete normally and write to the address after the block

erase command is executed.

Full status check

FMR06 = 1

and

FMR07 = 1?

FMR06 = 1?

Full status check completed

Yes

Command sequence error

Erase error

Program error

Command sequence error

Execute the clear status register command

(set these status flags to 0)

Check if the command is properly input

Re-execute the command

Erase error

Execute the clear status register command

(set these status flags to 0)

Erase command

re-execution times

≤ 3 times?

Re-execute the block erase command

Program error

Execute the clear status register command

(set these status flags to 0)

Specify an address other than

the write address where the error occurs

as the program address(1)

Re-execute the program command

Block targeting for erasure

cannot be used

Yes

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