H83687 datasheet(73/536 Pages) RENESAS

73 / 536 page

Section 2 CPU

Rev.5.00 Nov. 02, 2005 Page 41 of 500

REJ09B0027-0500

Reset state

Program halt state

Exception-handling state

Program execution state

Reset cleared

SLEEP instruction executed

Reset

occurs

Interrupt

source

Reset

occurs

Interrupt

source

Exception-

handling

complete

Reset occurs

Figure 2.12 State Transitions

2.8

Usage Notes

2.8.1

Notes on Data Access to Empty Areas

The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip

I/O registers areas available to the user. When data is transferred from CPU to empty areas, the

transferred data will be lost. This action may also cause the CPU to malfunction. When data is

transferred from an empty area to CPU, the contents of the data cannot be guaranteed.

2.8.2

EEPMOV Instruction

EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L,

which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so

that the end address of the destination address (value of R6

+ R4L) does not exceed H'FFFF (the

value of R6 must not change from H'FFFF to H'0000 during execution).

2.8.3

Bit-Manipulation Instruction

The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in

byte units, manipulate the data of the target bit, and write data to the same address again in byte

units. Special care is required when using these instructions in cases where two registers are

assigned to the same address, or when a bit is directly manipulated for a port or a register

containing a write-only bit, because this may rewrite data of a bit other than the bit to be

manipulated.

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