R5F72115D160FPV datasheet(520/1228 Pages) RENESAS

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Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 May. 08, 2008 Page 496 of 1200

REJ09B0344-0200

• Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing

in Complementary PWM Mode

An example of the procedure for setting output waveform control at synchronous counter

clearing in complementary PWM mode is shown in figure 10.57.

Stop count operation

Output waveform control at

synchronous counter clearing

Set TWCR and

complementary PWM mode

Start count operation

Output waveform control at

synchronous counter clearing

[1]

[2]

[3]

[1] Clear bits CST3 and CST4 in the timer

start register (TSTR) to 0, and halt timer

counter (TCNT) operation. Perform

TWCR setting while TCNT_3 and

TCNT_4 are stopped.

[2] Read bit WRE in TWCR and then write 1

to it to suppress initial value output at

counter clearing.

[3] Set bits CST3 and CST4 in TSTR to 1 to

start count operation.

Figure 10.57 Example of Procedure for Setting Output Waveform Control at Synchronous

Counter Clearing in Complementary PWM Mode

• Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary

PWM Mode

Figures 10.58 to 10.61 show examples of output waveform control in which the MTU2

operates in complementary PWM mode and synchronous counter clearing is generated while

the WRE bit in TWCR is set to 1. In the examples shown in figures 10.58 to 10.61,

synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 10.56,

respectively.

In the MTU2S, these examples are equivalent to the cases when the MTU2S operates in

complementary PWM mode and synchronous counter clearing is generated while the SCC bit

is cleared to 0 and the WRE bit is set to 1 in TWCR.

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