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R5F72115D160FPV Datasheet(PDF) 525 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 525 Page - Renesas Technology Corp

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Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 2.00 May. 08, 2008 Page 501 of 1200
REJ09B0344-0200
(o)
Suppressing MTU2–MTU2S Synchronous Counter Clearing
In the MTU2S, setting the SCC bit in TWCR to 1 suppresses synchronous counter clearing caused
by the MTU2.
Synchronous counter clearing is suppressed only within the interval shown in figure 10.62. When
using this function, the MTU2S should be set to complementary PWM mode.
For details of synchronous clearing caused by the MTU2, refer to the description about MTU2S
counter clearing caused by MTU2 flag setting source (MTU2-MTU2S synchronous counter
clearing) in section 10.4.10, MTU2–MTU2S Synchronous Operation.
Tb interval
at the crest
Tb interval
at the trough
Tb interval
at the crest
Tb interval
at the trough
TGRA_3
TGRB_3
TCDR
TDDR
H'0000
Tb interval
immediately
after counter
operation starts
MTU2-MTU2S synchronous counter
clearing is suppressed.
MTU2-MTU2S synchronous counter
clearing is suppressed.
Figure 10.62 MTU2–MTU2S Synchronous Clearing-Suppressed Interval Specified by SCC
Bit in TWCR



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