R5F72115D160FPV datasheet(526/1228 Pages) RENESAS

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Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 May. 08, 2008 Page 502 of 1200

REJ09B0344-0200

• Example of Procedure for Suppressing MTU2–MTU2S Synchronous Counter Clearing

An example of the procedure for suppressing MTU2–MTU2S synchronous counter clearing is

shown in figure 10.63.

Stop count operation (MTU2 and MTU2S)

MTU2-MTU2S synchronous counter

clearing suppress

Start count operation (MTU2 and MTU2S)

Output waveform control at

synchronous counter clearing and

synchronous counter clearing suppress

[1]

[3]

• Set the following.

• Complementary PWM mode (MTU2S)

• Compare match/input capture

operation (MTU2)

• Bit WRE in TWCR (MTU2S)

[2]

Set bit SCC in TWCR (MTU2S)

[4]

[1] Clear bits CST of the timer start register (TSTR) in the MTU2S

to 0, and halt count operation. Clear bits CST of TSTR in the

MTU2 to 0, and halt count operation.

[2] Set the complementary PWM mode in the MTU2S and

compare match/input capture operation in the MTU2. When bit

WRE in TWCR should be set, make appropriate setting here.

[3] Set bits CST3 and CST4 of TSTR in the MTU2S to 1 to start

count operation. For MTU2-MTU2S synchronous counter

clearing, set bits CST of TSTR in the MTU2 to 1 to start count

operation in any one of TCNT_0 to TCNT_2.

[4] Read TWCR and then set bit SCC in TWCR to 1 to suppress

MTU2-MTU2S synchronous counter clearing*. Here, do not

modify the CCE and WRE bit values in TWCR of the MTU2S.

MTU2-MTU2S synchronous counter clearing is suppressed in

the intervals shown in figure 10.62.

Note: * The SCC bit value can be modified during counter

operation. However, if a synchronous clearing occurs

when bit SCC is modified from 0 to 1, the synchronous

clearing may not be suppressed. If a synchronous

clearing occurs when bit SCC is modified from 1 to 0, the

synchronous clearing may be suppressed.

Figure 10.63 Example of Procedure for Suppressing MTU2–MTU2S Synchronous Counter

Clearing

• Examples of Suppression of MTU2–MTU2S Synchronous Counter Clearing

Figures 10.64 to 10.67 show examples of operation in which the MTU2S operates in

complementary PWM mode and MTU2–MTU2S synchronous counter clearing is suppressed

by setting the SCC bit in TWCR in the MTU2S to 1. In the examples shown in figures 10.64 to

10.67, synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure

10.56, respectively.

In these examples, the WRE bit in TWCR of the MTU2S is set to 1.

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