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R5F72115D160FPV Datasheet(PDF) 563 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 563 Page - Renesas Technology Corp |
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563 / 1228 page ![]() Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 2.00 May. 08, 2008 Page 539 of 1200 REJ09B0344-0200 P φ External clock TCNT input clock TCNT Rising edge Falling edge N - 1 N N - 1 Figure 10.96 Count Timing in External Clock Operation (Phase Counting Mode) (2) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10.97 shows output compare output timing (normal mode and PWM mode) and figure 10.98 shows output compare output timing (complementary PWM mode and reset synchronous PWM mode). TGR TCNT TCNT input clock N N N + 1 Compare match signal TIOC pin P φ Figure 10.97 Output Compare Output Timing (Normal Mode/PWM Mode) |
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