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R5F72115D160FPV Datasheet(PDF) 572 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 572 Page - Renesas Technology Corp |
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572 / 1228 page ![]() Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 2.00 May. 08, 2008 Page 548 of 1200 REJ09B0344-0200 Underflow signal TCNT (underflow) TCNT input clock H'0000 H'FFFF TCFU flag TCIU interrupt P φ Figure 10.114 TCIU Interrupt Setting Timing (4) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMAC is activated, the flag is cleared automatically. Figures 10.115 and 116 show the timing for status flag clearing by the CPU, and figure 10.117 shows the timing for status flag clearing by the DMAC. Status flag Write signal Address TSR address Interrupt request signal TSR write cycle T1 T2 P φ Figure 10.115 Timing for Status Flag Clearing by CPU (Channels 0 to 4) |
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