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R5F72115D160FPV Datasheet(PDF) 574 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 574 Page - Renesas Technology Corp |
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574 / 1228 page  Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 2.00 May. 08, 2008 Page 550 of 1200 REJ09B0344-0200 10.7 Usage Notes 10.7.1 Module Standby Mode Setting MTU2 operation can be disabled or enabled using the standby control register. The initial setting is for MTU2 operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 23, Power-Down Modes. 10.7.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The MTU2 will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.118 shows the input clock conditions in phase counting mode. Overlap Phase differ- ence Phase differ- ence Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap Pulse width : 1.5 states or more : 2.5 states or more Figure 10.118 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode |
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