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R5F72115D160FPV Datasheet(PDF) 1122 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 1122 Page - Renesas Technology Corp |
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1122 / 1228 page ![]() Section 27 Electrical Characteristics Rev. 2.00 May. 08, 2008 Page 1098 of 1200 REJ09B0344-0200 B φ = 40 MHz*1 Item Symbol Min. Max. Unit Figure CAS delay time 1 t CASD1 1 20 ns Figures 27.20 to 27.36 CAS delay time 2 t CASD2 1/2t cyc 1/2t cyc + 20 ns Figures 27.37, 27.38 DQM delay time 1 t DQMD1 1 20 ns Figures 27.20 to 27.33 DQM delay time 2 t DQMD2 1/2t cyc 1/2t cyc + 20 ns Figures 27.37, 27.38 CKE delay time 1 t CKED1 1 20 ns Figure 27.35 CKE delay time 2 t CKED2 1/2t cyc 1/2t cyc + 20 ns Figure 27.38 AH delay time t AHD 1/2t cyc 1/2t cyc + 20 ns Figure 27.16 Multiplexed address delay time t MAD — 20 ns Figure 27.16 Multiplexed address hold time t MAH 1 — ns Figure 27.16 DACK, TEND delay time t DACD — Refer to peripheral modules ns Figures 27.12 to 27.33, 27.37 Note: * The maximum value (f max) of Bφ (external bus clock) depends on the number of wait cycles and the system configuration of your board. |
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