H8SXSLASH1657C datasheet(17/892 Pages) RENESAS

17 / 892 page

Rev. 2.00 Jun. 28, 2007 Page xvii of xxiv

10.3.1 Timer Control Register (TCR).............................................................................. 412

10.3.2 Timer Mode Register (TMDR) ............................................................................. 417

10.3.3 Timer I/O Control Register (TIOR) ...................................................................... 418

10.3.4 Timer Interrupt Enable Register (TIER) ............................................................... 436

10.3.5 Timer Status Register (TSR)................................................................................. 438

10.3.6 Timer Counter (TCNT)......................................................................................... 442

10.3.7 Timer General Register (TGR) ............................................................................. 442

10.3.8 Timer Start Register (TSTR) ................................................................................ 443

10.3.9 Timer Synchronous Register (TSYR)................................................................... 444

10.4

Operation ........................................................................................................................... 445

10.4.1 Basic Functions..................................................................................................... 445

10.4.2 Synchronous Operation......................................................................................... 451

10.4.3 Buffer Operation ................................................................................................... 453

10.4.4 Cascaded Operation .............................................................................................. 457

10.4.5 PWM Modes ......................................................................................................... 459

10.4.6 Phase Counting Mode ........................................................................................... 464

10.5

Interrupt Sources................................................................................................................ 471

10.6

DTC Activation..................................................................................................................473

10.7

DMAC Activation.............................................................................................................. 473

10.8

A/D Converter Activation.................................................................................................. 473

10.9

Operation Timing............................................................................................................... 474

10.9.1 Input/Output Timing ............................................................................................. 474

10.9.2 Interrupt Signal Timing......................................................................................... 478

10.10 Usage Notes ....................................................................................................................... 482

10.10.1 Module Stop State Setting .................................................................................... 482

10.10.2 Input Clock Restrictions ....................................................................................... 482

10.10.3 Caution on Cycle Setting ...................................................................................... 483

10.10.4 Conflict between TCNT Write and Clear Operations........................................... 483

10.10.5 Conflict between TCNT Write and Increment Operations ................................... 484

10.10.6 Conflict between TGR Write and Compare Match............................................... 484

10.10.7 Conflict between Buffer Register Write and Compare Match .............................. 485

10.10.8 Conflict between TGR Read and Input Capture ................................................... 485

10.10.9 Conflict between TGR Write and Input Capture .................................................. 486

10.10.10 Conflict between Buffer Register Write and Input Capture ............................... 487

10.10.11 Conflict between Overflow/Underflow and Counter Clearing........................... 487

10.10.12 Conflict between TCNT Write and Overflow/Underflow.................................. 488

10.10.13 Multiplexing of I/O Pins .................................................................................... 489

10.10.14 Interrupts in Module Stop State.......................................................................... 489

H8SX/1657C Datasheet(PDF) 17 Page - Renesas Technology Corp

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