H8SXSLASH1658R datasheet(17/1374 Pages) RENESAS

17 / 1374 page

Rev. 2.00 Sep. 25, 2008 Page xvii of xxx

Section 12 Data Transfer Controller (DTC) ......................................................467

12.1

Features............................................................................................................................. 467

12.2

Register Descriptions ........................................................................................................ 469

12.2.1

DTC Mode Register A (MRA) ......................................................................... 470

12.2.2

DTC Mode Register B (MRB).......................................................................... 471

12.2.3

DTC Source Address Register (SAR)............................................................... 472

12.2.4

DTC Destination Address Register (DAR)....................................................... 473

12.2.5

DTC Transfer Count Register A (CRA) ........................................................... 473

12.2.6

DTC Transfer Count Register B (CRB)............................................................ 474

12.2.7

DTC enable registers A to F (DTCERA to DTCERF)...................................... 474

12.2.8

DTC Control Register (DTCCR) ...................................................................... 475

12.2.9

DTC Vector Base Register (DTCVBR)............................................................ 477

12.3

Activation Sources............................................................................................................ 477

12.4

Location of Transfer Information and DTC Vector Table ................................................ 477

12.5

Operation .......................................................................................................................... 482

12.5.1

Bus Cycle Division ........................................................................................... 484

12.5.2

Transfer Information Read Skip Function ........................................................ 486

12.5.3

Transfer Information Writeback Skip Function ................................................ 487

12.5.4

Normal Transfer Mode ..................................................................................... 487

12.5.5

Repeat Transfer Mode....................................................................................... 488

12.5.6

Block Transfer Mode ........................................................................................ 490

12.5.7

Chain Transfer .................................................................................................. 491

12.5.8

Operation Timing.............................................................................................. 492

12.5.9

Number of DTC Execution Cycles ................................................................... 494

12.5.10

DTC Bus Release Timing ................................................................................. 495

12.5.11

DTC Priority Level Control to the CPU ........................................................... 495

12.6

DTC Activation by Interrupt............................................................................................. 496

12.7

Examples of Use of the DTC ............................................................................................ 497

12.7.1

Normal Transfer Mode ..................................................................................... 497

12.7.2

Chain Transfer .................................................................................................. 497

12.7.3

Chain Transfer when Counter = 0..................................................................... 498

12.8

Interrupt Sources...............................................................................................................500

12.9

Usage Notes ...................................................................................................................... 500

12.9.1

Module Stop State Setting ................................................................................ 500

12.9.2

On-Chip RAM .................................................................................................. 500

12.9.3

DMAC Transfer End Interrupt.......................................................................... 500

12.9.4

DTCE Bit Setting.............................................................................................. 500

12.9.5

Chain Transfer .................................................................................................. 501

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