M16CSLASH29 datasheet(466/499 Pages) RENESAS

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22. Usage Notes

page 442

22.11 CAN Module

22.11.1 Reading C0STR Register

The CAN module on the M16C/29 Group updates the status of the C0STR register in a certain period.

When the CPU and the CAN module access to the C0STR register at the same time, the CPU has the

access priority; the access from the CAN module is disabled. Consequently, when the updating period of

the CAN module matches the access period from the CPU, the status of the CAN module cannot be

updated. (See Figure 22.5)

Accordingly, be careful about the following points so that the access period from the CPU should not

match the updating period of the CAN module:

(1) There should be a wait time of 3fCAN or longer (see Table 22.2) before the CPU reads the C0STR

(2) When the CPU polls the C0STR register, the polling period must be 3fCAN or longer. (See Figure

22.7

)

Table 22.2 CAN Module Status Updating Period

3fCAN period = 3 ✕ XIN (Original oscillation period) ✕ Division value of the CAN clock (CCLK)

(Example 1) Condition XIN 16 MHz CCLK: Divided by 1

3fCAN period = 3 ✕ 62.5 ns ✕ 1 = 187.5 ns

(Example 2) Condition XIN 16 MHz CCLK: Divided by 2

3fCAN period = 3 ✕ 62.5 ns ✕ 2 = 375 ns

(Example 3) Condition XIN 16 MHz CCLK: Divided by 4

3fCAN period = 3 ✕ 62.5 ns ✕ 4 = 750 ns

(Example 4) Condition XIN 16 MHz CCLK: Divided by 8

3fCAN period = 3 ✕ 62.5 ns ✕ 8 = 1.5 µs

(Example 5) Condition XIN 16 MHz CCLK: Divided by 16

3fCAN period = 3 ✕ 62.5 ns ✕ 16 = 3 µs

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