M32CSLASH8A datasheet(351/372 Pages) RENESAS

351 / 372 page

M32C/8A Group

24. Usage Notes

Rev.1.00

Jul 15, 2007

Page 334 of 352

REJ09B0385-0100

24.3

Clock Generation Circuits

24.3.1

Main Clock

• When the CPU operating frequency is required 24 MHz or more, make an oscillator connected to the main

clock circuit (XIN-XOUT), or an external clock applied to the XIN pin have 24 MHz or less frequency, and

then multiply the main clock with the PLL frequency synthesizer. By using this procedure, a better EMC

(Electromagnetic Compatibility) performance can be achieved than using a more than 24 MHz oscillator

(external clock).

• If the main clock is selected as the CPU clock while an external clock is applied to the XIN pin, do not stop

the external clock.

(Technical update: TN-M16C-109-0309)

• When an external clock is used for the CPU clock, do not set the CM05 bit in the CM0 register to 1

(stopped).

24.3.2

Sub Clock

24.3.2.1

To Oscillate Sub Clock

To oscillate the sub clock, set the CM07 bit in the CM0 register to 0 (clock other than the sub clock) and the

CM03 bit to 1 (XCIN-XOUT drive capability HIGH). Then, set the CM04 bit in the CM0 register to 1 (XCIN-

XCOUT oscillation function). Once the sub clock becomes stabilized, set the CM03 bit to 0 (XCIN-XOUT

drive capability LOW).

After the above procedure, the sub clock can be used as the CPU clock, or the count source for timer A and

timer B.

(Technical update: TN-16C-119A/EA)

24.3.2.2

Oscillation Parameter Matching

If an oscillation circuit constant matching for the sub clock oscillation circuit has only been evaluated with the

drive capability HIGH, the constant matching for drive capability LOW must also be evaluated.

Contact your oscillator manufacturer for details on the oscillation circuit constant matching.

24.3.3

Clock Dividing Ratio

To change bits MCD4 to MCD0, set the PM12 bit in the PM1 register to 0 (no wait state).

24.3.4

Power Consumption Control

Stabilize the main clock, sub clock, or PLL clock prior to switching the clock source for the CPU clock to one

of these clocks.

24.3.4.1

Wait Mode

• When entering wait mode with setting the CM02 bit in the CM0 register to 1 (peripheral clocks stop in wait

mode), set bits MCD4 to MCD0 in the MCD register to be the 10-MHz or less CPU clock frequency after

dividing the main clock.

• When entering wait mode, the instructions following the WAIT instruction are stored into the instruction

queue, and the program stops. Insert at least 4 NOP instructions after the WAIT instruction.

• To enter wait mode, execute the WAIT instruction while a high-level (“H”) signal is applied to the NMI

pin.

M32C/8A Datasheet(PDF) 351 Page - Renesas Technology Corp

M32C/8A Datasheet(HTML) 351 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL