M32CSLASH8A datasheet(355/372 Pages) RENESAS

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M32C/8A Group

24. Usage Notes

Rev.1.00

Jul 15, 2007

Page 338 of 352

REJ09B0385-0100

24.5

Interrupts

24.5.1

ISP Setting

After reset, ISP is initialized to 000000h. The program crash may occur if an interrupt is acknowledged before

setting a value to ISP. Therefore, ISP must be set before any interrupt request is acknowledged. Setting ISP to

an even address allows interrupt sequences to be executed at a higher speed.

To use the NMI interrupt, set ISP at the very beginning of the program. The NMI interrupt can be

acknowledged after the first instruction has been executed after reset.

24.5.2

NMI Interrupt

• The NMI interrupt cannot be disabled. Connect the NMI pin to VCC1 via a resistor (pull-up) when not in

use.

• The P8_5 bit in the P8 register indicates the voltage level applied to the NMI pin. Read the P8_5 bit only to

determine the pin level after the NMI interrupt occurs.

24.5.3

INT Interrupt

• Edge Sensitive

Each of “H” or “L” width of signals applied to pins INT0 to INT5 must be 250 ns or more regardless of the

CPU clock frequency.

• Level Sensitive

Each of “H” or “L” width of signals applied to pins INT0 to INT5 must be one CPU clock cycle + 200 ns or

more. For example, each of “H” or “L” width must be 234 ns or more if the CPU clock is 30 MHz.

• The IR bit in the INTiIC register (i = 0 to 5) may become 1 (interrupt requested) when the polarity settings of

pins INT0 to INT5 are changed. Set the IR bit to 0 (interrupt not requested) after the polarity setting is changed.

Figure 24.3 shows an example of the switching procedure for an INTi interrupt source (i = 0 to 5).

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