H838532H datasheet(351/508 Pages) RENESAS

351 / 508 page

Section 10 Serial Communication Interface

Rev. 1.00 May 30, 2008 Page 331 of 484

REJ09B0436-0100

SCI3 operates as follows when receiving data.

SCI3 performs internal synchronization and begins reception in synchronization with the serial

clock input or output.

The received data is placed in RSR in LSB-to-MSB order.

After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive

data can be transferred from RSR to RDR.

If this check shows that there is no overrun error, bit RDRF is set to 1, and the receive data is

stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the check identifies

an overrun error, bit OER is set to 1.

Bit RDRF remains set to 1. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.

See table 10.12 for the conditions for detecting a receive error, and receive data processing.

Note:

No further receive operations are possible while a receive error flag is set. Bits OER, FER,

PER, and RDRF must therefore be cleared to 0 before resuming reception.

Figure 10.14 shows an example of the operation when receiving in synchronous mode.

Serial

clock

Serial

data

Bit 0

Bit 7

Bit 0

1 frame

Bit 1

Bit 6

Bit 7

RDRF

OER

LSI

operation

User

processing

RXI request

RDR data read

RDRE cleared

to 0

RXI request

ERI request in

response to

overrun error

Overrun error

processing

RDR data has

not been read

(RDRF = 1)

Figure 10.14 Example of Operation when Receiving in Synchronous Mode

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