H838532H datasheet(364/508 Pages) RENESAS

364 / 508 page

Section 11 14-Bit PWM

Rev. 1.00 May 30, 2008 Page 344 of 484

REJ09B0436-0100

Bits 1 and 0: Clock select 1 and 0 (PWCR1, PWCR0)

Bits 1 and 0 select the clock supplied to the 14-bit PWM. These bits are write-only bits; they are

always read as 1.

Bit 1

PWCR1

Bit 0

PWCR0

Description

The input clock is

φ/2 (tφ* = 2/φ)

(initial value)

The conversion period is 16,384/

φ, with a minimum

modulation width of 1/

The input clock is

φ/4 (tφ* = 4/φ)

The conversion period is 32,768/

φ, with a minimum

modulation width of 2/

The input clock is

φ/8 (tφ* = 8/φ)

The conversion period is 65,536/

φ, with a minimum

modulation width of 4/

The input clock is

φ/16 (tφ* = 16/φ)

The conversion period is 131,072/

φ, with a minimum

modulation width of 8/

Note:

Period of PWM input clock.

11.2.2

PWM Data Registers U and L (PWDRU, PWDRL)

Bit

Initial value

Read/Write

—

PWDRU5

PWDRU4

PWDRU3

PWDRU0

PWDRU2

PWDRU1

PWDRU

Bit

Initial value

Read/Write

PWDRL7

PWDRL6

PWDRL5

PWDRL4

PWDRL3

PWDRL0

PWDRL2

PWDRL1

PWDRL

PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU

and the lower 8 bits to PWDRL. The value written to PWDRU and PWDRL gives the total high-

level width of one PWM waveform cycle.

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