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H838532H Datasheet(PDF) 366 Page - Renesas Technology Corp |
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H838532H Datasheet(HTML) 366 Page - Renesas Technology Corp |
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366 / 508 page ![]() Section 11 14-Bit PWM Rev. 1.00 May 30, 2008 Page 346 of 484 REJ09B0436-0100 11.3 Operation 11.3.1 Operation When using the 14-bit PWM, set the registers in the following sequence. 1. Set bit PWM in port mode register 3 (PMR3) to 1 so that pin P3 0/PWM is designated for PWM output. 2. Set bits PWCR1 and PWCR0 in the PWM control register (PWCR) to select a conversion period of 131,072/ φ (PWCR1 = 1, PWCR0 = 1), 65,536/φ (PWCR1 = 1, PWCR0 = 0), 32,768/ φ (PWCR1 = 0, PWCR0 = 1), or 16,384/φ (PWCR1 = 0, PWCR0 = 0). 3. Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write in the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the data in these registers will be latched in the PWM waveform generator, updating the PWM waveform generation in synchronization with internal signals. One conversion period consists of 64 pulses, as shown in figure 11.2. The total of the high-level pulse widths during this period (T H) corresponds to the data in PWDRU and PWDRL. This relation can be represented as follows. T H = (data value in PWDRU and PWDRL + 64) × t φ/2 where t φ is the PWM input clock period: 2/φ (PWCR = H'0), 4/φ (PWCR = H'1), 8/φ (PWCR = H'2), or 16/ φ (PWCR = H'3). Example: Settings in order to obtain a conversion period of 32,768 µs: When PWCR1 = 0 and PWCR0 = 0, the conversion period is 16,384/ φ, so φ must be 0.5 MHz. In this case, tfn = 512 µs, with 1/ φ (resolution) = 2.0 µs. When PWCR1 = 0 and PWCR0 = 1, the conversion period is 32,768/ φ, so φ must be 1 MHz. In this case, tfn = 512 µs, with 2/ φ (resolution) = 2.0 µs. When PWCR1 = 1 and PWCR0 = 0, the conversion period is 65,536/ φ , so φ must be 2 MHz. In this case, tfn = 512 µs, with 4/ φ (resolution) = 2.0 µs. Accordingly, for a conversion period of 32,768 µs, the system clock frequency ( φ) must be 0.5 MHz, 1 MHz, or 2 MHz. |
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