H838532H datasheet(402/508 Pages) RENESAS

402 / 508 page

Section 13 LCD Controller/Driver

Rev. 1.00 May 30, 2008 Page 382 of 484

REJ09B0436-0100

13.3.4

Low-Power-Consumption LCD Drive System

The use of the built-in split-resistance is normally the easiest method for implementing the LCD

power supply circuit, but since the built-in resistance is fixed, a certain direct current flows

constantly from the built-in resistance’s V

CC to VSS. As this current does not depend on the current

dissipation of the LCD panel, if an LCD panel with a small current dissipation is used, a wasteful

amount of power will be consumed. This LSI is equipped with a function to minimize this waste

of power. Use of this function makes it possible to achieve the optimum power supply circuit for

the LCD panel’s current dissipation.

(1) Principles

a. Capacitors are connected as external circuits to LCD power supply pins V1, V2, and V3, as

shown in figure 13.10.

b. The capacitors connected to V1, V2, and V3 are repeatedly charged and discharged in the

cycle shown in figure 13.10, maintaining the potentials.

c. At this time, the charged potential is a potential corresponding to the V1, V2, and V3 pins,

respectively. (For example, with 1/3 bias drive, the charge for V2 is 2/3 that of V1, and that for

V3 is 1/3 that of V1.)

d. Power is supplied to the LCD panel by means of the charges accumulated in these capacitors.

e. The capacitances and charging/discharging periods of these capacitors are therefore

determined by the current dissipation of the LCD panel.

f. The charging and discharging periods can be selected by software.

(2) Example of Operation (with 1/3 bias drive)

a. During charging period Tc in the figure, the potential is divided among pins V1, V2, and V3

by the built-in split-resistance (the potential of V2 being 2/3 that of V1, and that of V3 being

1/3 that of V1), as shown in figure 13.10, and external capacitors C1, C2, and C3 are charged.

The LCD panel is continues to be driven during this time.

b. In the following discharging period, Tdc, charging is halted and the charge accumulated in

each capacitor is discharged, driving the LCD panel.

c. At this time, a slight voltage drop occurs due to the discharging; optimum values must be

selected for the charging period and the capacitor capacitances to ensure that this does not

affect the driving of the LCD panel.

d. In this way, the capacitors connected to V1, V2, and V3 are repeatedly charged and discharged

in the cycle shown in figure 13.10, maintaining the potentials and continuously driving the

LCD panel.

H838532H Datasheet(PDF) 402 Page - Renesas Technology Corp