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H838532H Datasheet(PDF) 406 Page - Renesas Technology Corp |
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H838532H Datasheet(HTML) 406 Page - Renesas Technology Corp |
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406 / 508 page ![]() Section 13 LCD Controller/Driver Rev. 1.00 May 30, 2008 Page 386 of 484 REJ09B0436-0100 Table 13.3 Output Levels Data 0 0 1 1 M 0 1 0 1 Static Common output V 1 V SS V 1 V SS Segment output V 1 V SS V SS V 1 1/2 duty Common output V 2, V3 V 2, V3 V 1 V SS Segment output V 1 V SS V SS V 1 1/3 duty Common output V 3 V 2 V 1 V SS Segment output V 2 V 3 V SS V 1 1/4 duty Common output V 3 V 2 V 1 V SS Segment output V 2 V 3 V SS V 1 13.3.5 Operation in Power-Down Modes In this LSI, the LCD controller/driver can be operated even in the power-down modes. The operating state of the LCD controller/driver in the power-down modes is summarized in table 13.4. In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and therefore, unless φw, φw/2, or φw/4 has been selected by bits CKS3 to CKS0, the clock will not be supplied and display will halt. Since there is a possibility that a direct current will be applied to the LCD panel in this case, it is essential to ensure that φw, φw/2, or φw/4 is selected. In active (medium-speed) mode, the system clock is switched, and therefore CKS3 to CKS0 must be modified to ensure that the frame frequency does not change. |
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