H838532H datasheet(271/508 Pages) RENESAS

271 / 508 page

Section 9 Timers

Rev. 1.00 May 30, 2008 Page 251 of 484

REJ09B0436-0100

Bits 3 and 2: Counter clear 1 and 0 (CCLR1, CCLR0)

Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges

of the input capture input signal.

Bit 3

CCLR1

Bit 2

CCLR0

Description

TCG clearing is disabled

(initial value)

TCG cleared by falling edge of input capture input signal

TCG cleared by rising edge of input capture input signal

TCG cleared by both edges of input capture input signal

Bits 1 and 0: Clock select (CKS1, CKS0)

Bits 1 and 0 select the clock input to TCG from among four internal clock sources.

Bit 1

CKS1

Bit 0

CKS0

Description

Internal clock: Counting on

φ/64

(initial value)

Internal clock: Counting on

φ/32

Internal clock: Counting on

φ/2

Internal clock: Counting on

φw/4

(5) Clock Stop Register 1 (CKSTPR1)

—

TFCKSTP TCCKSTP TACKSTP

S31CKSTP S32CKSTP ADCKSTP TGCKSTP

543210

1111111

R/W

Bit

Initial value

Read/Write

CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral

modules. Only the bit relating to timer G is described here. For details of the other bits, see the

sections on the relevant modules.

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