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H838532H Datasheet(PDF) 295 Page - Renesas Technology Corp |
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H838532H Datasheet(HTML) 295 Page - Renesas Technology Corp |
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295 / 508 page  Section 9 Timers Rev. 1.00 May 30, 2008 Page 275 of 484 REJ09B0436-0100 (4) Register Configuration Table 9.20 shows the register configuration of the asynchronous event counter. Table 9.20 Asynchronous Event Counter Registers Name Abbr. R/W Initial Value Address Event counter control/status register ECCSR R/W H'00 H'FF95 Event counter H ECH R H'00 H'FF96 Event counter L ECL R H'00 H'FF97 Clock stop register 2 CKSTPR2 R/W H'FF H'FFFB 9.7.2 Register Descriptions (1) Event Counter Control/Status Register (ECCSR) OVH CUEL CRCH CRCL OVL — CH2 CUEH 76543210 0 000 00 00 R/W* R/W R/W R/W R/W* R/W R/W R/W Bit Note: * Bits 7 and 6 can only be written with 0, for flag clearing. Initial Value Read/Write ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting, and halting of the count-up function. ECCSR is initialized to H'00 upon reset. |
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