H838532H datasheet(298/508 Pages) RENESAS

298 / 508 page

Section 9 Timers

Rev. 1.00 May 30, 2008 Page 278 of 484

REJ09B0436-0100

Bit 1: Counter reset control H (CRCH)

Bit 1 controls resetting of ECH. When this bit is cleared to 0, ECH is reset. When 1 is written to

this bit, the counter reset is cleared and the ECH count-up function is enabled.

Bit 1

CRCH

Description

ECH is reset

(initial value)

ECH reset is cleared and count-up function is enabled

Bit 0: Counter reset control L (CRCL)

Bit 0 controls resetting of ECL. When this bit is cleared to 0, ECL is reset. When 1 is written to

this bit, the counter reset is cleared and the ECL count-up function is enabled.

Bit 0

CRCL

Description

ECL is reset

(initial value)

ECL reset is cleared and count-up function is enabled

(2) Event Counter H (ECH)

ECH7

ECH2

ECH1

ECH0

ECH6

ECH5

ECH4

ECH3

76543210

000

RRR

Bit

Initial Value

Read/Write

ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or

as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL. Either

the external asynchronous event AEVH pin or the overflow signal from lower 8-bit counter ECL

can be selected as the input clock source by bit CH2. ECH can be cleared to H'00 by software, and

is also initialized to H'00 upon reset.

H838532H Datasheet(PDF) 298 Page - Renesas Technology Corp