H838532H datasheet(302/508 Pages) RENESAS

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Section 9 Timers

Rev. 1.00 May 30, 2008 Page 282 of 484

REJ09B0436-0100

9.7.4

Asynchronous Event Counter Operation Modes

Asynchronous event counter operation modes are shown in table 9.21.

Table 9.21

Asynchronous Event Counter Operation Modes

Operation Mode

Reset

Active

Sleep

Watch

Sub-

active

Sub-

sleep

Standby

Module

Standby

ECCSR

Reset

Functions Functions

Held*

Functions Functions Held*

Held

ECH

Reset

Functions Functions

Functions* Functions Functions Functions* Halted

ECL

Reset

Functions Functions

Functions* Functions Functions Functions* Halted

Note:

When an asynchronous external event is input, the counter increments but the counter

overflow H/L flags are not affected.

9.7.5

Application Notes

1. When reading the values in ECH and ECL, the correct value will not be returned if the event

counter increments during the read operation. Therefore, if the counter is being used in the 8-

bit mode, clear bits CUEH and CUEL in ECCSR to 0 before reading ECH or ECL. If the

counter is being used in the 16-bit mode, clear CUEL only to 0 before reading ECH or ECL.

2. The maximum clock frequency to be input to the AEVH and AEVL pins is 16 MHz. In

addition, ensure that the high and low widths of the clock are at least 32 ns. The duty cycle is

immaterial.

Mode

Maximum AEVH/AEVL Pin

Input Clock Frequency

16-bit mode

8-bit mode

Active (high-speed), sleep (high-speed)

CC = 2.7 to 5.5 V/16 MHz

8-bit mode

Active (medium-speed), sleep (medium-speed) (

φ/16)

(

φ/32)

(

φ/64)

OSC = 1 MHz to 16 MHz

(

φ/128)

2 · f

OSC

1/2 · f

OSC

1/4 · f

OSC

8-bit mode

Watch, subactive, subsleep, standby

(

φw/2)

(

φw/4)

W = 32.768 kHz or 38.4 kHz

(

φw/8)

1000 kHz

500 kHz

250 kHz

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