H8S2245 datasheet(340/818 Pages) RENESAS

340 / 818 page

Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.3.00 Mar. 26, 2007 Page 298 of 772

REJ09B0355-0300

9.2.3

Timer I/O Control Register (TIOR)

IOB3

R/W

IOB2

R/W

IOB1

R/W

IOB0

R/W

IOA3

R/W

IOA0

R/W

IOA2

R/W

IOA1

R/W

Bit

Initial value

R/W

Channel 0: TIOR0H

Channel 1: TIOR1

Channel 2: TIOR2

IOD3

R/W

IOD2

R/W

IOD1

R/W

IOD0

R/W

IOC3

R/W

IOC0

R/W

IOC2

R/W

IOC1

R/W

Channel 0: TIOR0L

Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the

Bit

Initial value

R/W

The TIOR registers are 8-bit registers that control the TGR registers. The TPU has four TIOR

registers, two for channel 0 and one each for channels 1, and 2. The TIOR registers are initialized

to H'00 by a reset, and in hardware standby mode.

Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR

is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM

mode 2, the output at the point at which the counter is cleared to 0 is specified.

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