H8S2245 datasheet(352/818 Pages) RENESAS

352 / 818 page

Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.3.00 Mar. 26, 2007 Page 310 of 772

REJ09B0355-0300

The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has three

TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in

hardware standby mode.

Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT

counts in channels 1, and 2.

In channel 0 bit 7 is reserved. It is always read as 1 and cannot be modified.

Bit 7

TCFD

Description

TCNT counts down

TCNT counts up

(Initial value)

Bit 6—Reserved: Read-only bit, always read as 1.

Bit 5—Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred

when channels 1 and 2 are set to phase counting mode.

In channel 0 bit 5 is reserved. It is always read as 0 and cannot be modified.

Bit 5

TCFU

Description

[Clearing condition]

(Initial value)

When 0 is written to TCFU after reading TCFU = 1

[Setting condition]

When the TCNT value underflows (changes from H'0000 to H'FFFF)

Bit 4—Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred.

Bit 4

TCFV

Description

[Clearing condition]

(Initial value)

When 0 is written to TCFV after reading TCFV = 1

[Setting condition]

When the TCNT value overflows (changes from H'FFFF to H'0000 )

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