H8S2245 datasheet(374/818 Pages) RENESAS

374 / 818 page

Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.3.00 Mar. 26, 2007 Page 332 of 772

REJ09B0355-0300

• PWM mode 1

PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and

TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is

output from the TIOCA and TIOCC pins at compare matches A and C, and the output

specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B

and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired

TGRs are identical, the output value does not change when a compare match occurs.

In PWM mode 1, a maximum 4-phase PWM output is possible.

• PWM mode 2

PWM output is generated using one TGR as the cycle register and the others as duty registers.

The output specified in TIOR is performed by means of compare matches. Upon counter

clearing by a synchronization register compare match, the output value of each pin is the initial

value set in TIOR. If the set values of the cycle and duty registers are identical, the output

value does not change when a compare match occurs.

In PWM mode 2, a maximum 7-phase PWM output is possible by combined use with

synchronous operation.

The correspondence between PWM output pins and registers is shown in table 9.6.

Table 9.6

PWM Output Registers and Output Pins

Output Pins

Channel

Registers

PWM Mode 1

PWM Mode 2

TGR0A

TIOCA0

TGR0B

TIOCB0

TGR0C

TIOCC0

TGR0D

TIOCD0

TGR1A

TIOCA1

TGR1B

TIOCB1

TGR2A

TIOCA2

TGR2B

TIOCB2

Note:

In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.

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