H8S2245 datasheet(527/818 Pages) RENESAS

527 / 818 page

Section 13 Smart Card Interface

Rev.3.00 Mar. 26, 2007 Page 485 of 772

REJ09B0355-0300

The operation sequence is as follows.

[1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-

up resistor.

[2] The transmitting station starts transfer of one frame of data. The data frame starts with a start

bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).

[3] With the Smart Card interface, the data line then returns to the high-impedance state. The data

line is pulled high with a pull-up resistor.

[4] The receiving station carries out a parity check.

If there is no parity error and the data is received normally, the receiving station waits for

reception of the next data.

If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level)

to request retransmission of the data. After outputting the error signal for the prescribed length

of time, the receiving station places the signal line in the high-impedance state again. The

signal line is pulled high again by a pull-up resistor.

[5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data

frame.

If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous

data.

13.3.4

Table 13.3 shows a bit map of the registers used by the smart card interface.

Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described

below.

H8S2245 Datasheet(PDF) 527 Page - Renesas Technology Corp