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H8S2245 Datasheet(PDF) 572 Page - Renesas Technology Corp |
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H8S2245 Datasheet(HTML) 572 Page - Renesas Technology Corp |
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572 / 818 page  Section 16 ROM Rev.3.00 Mar. 26, 2007 Page 530 of 772 REJ09B0355-0300 16.1.1 Block Diagram Figure 16.1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'01FFFE H'000001 H'000003 H'01FFFF H'00FFFE H'010000 H'010002 H'00FFFF H'010001 H'010003 When EAE= 0 Figure 16.1 Block Diagram of ROM (Example with H8S/2246 and H8S/2245 in Modes 6, 7) 16.1.2 Register Configuration The on-chip ROM is controlled by BCRL. The register configuration is shown in table 16.1. Table 16.1 Register Configuration Initial Value Name Abbreviation R/W Power-On Reset Manual Reset Address* Bus control register L BCRL R/W H'3C Retained H'FED5 Note: * Lower 16 bits of the address. |
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