H8S2245 datasheet(573/818 Pages) RENESAS

573 / 818 page

Section 16 ROM

Rev.3.00 Mar. 26, 2007 Page 531 of 772

REJ09B0355-0300

16.2

16.2.1

Bus Control Register L (BCRL)

BRLE

R/W

BREQOE

R/W

EAE

R/W

—

R/W

—

R/W

WAITE

R/W

ASS

R/W

—

R/W

Bit

Initial value

R/W

BCRL is an 8-bit readable/writable register that performs selection of the external bus release state

protocol, selection of the area partition unit, and enabling or disabling of

WAIT pin input.

BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not

initialized by a manual reset or in software standby mode.

Enabling or disabling of part of the on-chip ROM area can be selected by means of the EAE bit in

BCRL. For details of the other bits in BCRL, see section 6.2.5, Bus Control Register L (BCRL).

Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF are

to be internal addresses or external addresses.

This setting is invalid in normal mode.

Bit 5

EAE

Description

Addresses H'010000 to H'01FFFF are in on-chip ROM (in the H8S/2246 and

H8S/2245) or a reserved area* (in the H8S/2244, H8S/2243, H8S/2242, and

H8S/2241).

Addresses H'010000 to H'01FFFF are external addresses (external expansion mode)

or a reserved area* (single-chip mode).

(Initial value)

Note:

Reserved areas should not be accessed.

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