H8S2245 datasheet(586/818 Pages) RENESAS

586 / 818 page

Section 17 Clock Pulse Generator

Rev.3.00 Mar. 26, 2007 Page 544 of 772

REJ09B0355-0300

17.1.2

The clock pulse generator is controlled by SCKCR and LPWCR. Table 17.1 shows the register

configuration.

Table 17.1

Clock Pulse Generator Register

Name

Abbreviation

R/W

Initial Value

Address*

System clock control register

SCKCR

R/W

H'00

H'FF3A

Low power control register

LPWCR

R/W

H'00

H'FF44

Note:

Lower 16 bits of the address.

17.2

17.2.1

System Clock Control Register (SCKCR)

PSTOP

R/W

—

R/W

—

SCK0

R/W

SCK2

R/W

SCK1

R/W

Bit

Initial value

R/W

SCKCR is an 8-bit readable/writable register that performs

φ clock output control and medium-

speed mode control.

SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—

φφφφ Clock Output Disable (PSTOP): Controls φ output.

Description

Bit 7

PSTOP

Normal Operation

Sleep Mode

Software

Standby Mode

Hardware

Standby Mode

φ output (initial value)

φ output

Fixed high

High impedance

Fixed high

High impedance

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