H8S2245 datasheet(587/818 Pages) RENESAS

587 / 818 page

Section 17 Clock Pulse Generator

Rev.3.00 Mar. 26, 2007 Page 545 of 772

REJ09B0355-0300

Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.

Bits 5 to 3—Reserved: Read-only bits, always read as 0.

Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus

master.

Bit 2

Bit 1

Bit 0

SCK2

SCK1

SCK0

Description

Bus master is in high-speed mode

(Initial value)

Medium-speed clock is

φ/2

Medium-speed clock is

φ/4

Medium-speed clock is

φ/8

Medium-speed clock is

φ/16

Medium-speed clock is

φ/32

1—

—

17.2.2

Low Power Control Register (LPWCR)

—

R/W

—

R/W

RFCUT

R/W

—

R/W

—

R/W

—

R/W

—

R/W

—

R/W

Bit

Initial value

R/W

LPWCR is an 8-bit readable/writable register that controls the oscillator's built-in feedback

resistor when using external clock input.

LPWCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 6 and 7—Reserved: These bits can be read or written to, but do not affect operation.

Bit 5—Built-in Feedback Resistor Control (RFCUT): Selects whether the oscillator's built-in

feedback resistor and duty adjustment circuit are used with external clock input. Do not access this

bit when a crystal oscillator is used.

When an external clock is input, a temporary transition should be made to software standby mode

after setting this bit. When software standby mode is entered, it is possible to select use or non-use

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