H8S2245 datasheet(591/818 Pages) RENESAS

591 / 818 page

Section 17 Clock Pulse Generator

Rev.3.00 Mar. 26, 2007 Page 549 of 772

REJ09B0355-0300

External Clock

The external clock signal should have the same frequency as the system clock (

φ).

Table 17.4 and figure 17.6 show the input conditions for the external clock.

Table 17.4

External Clock Input Conditions

CC = 2.7 V

to 5.5 V

CC = 2.7 V

to 5.5 V*

CC = 5.0 V

±10%

Item

Symbol

Min

Max

Min

Max

Min

Max

Unit

Test Conditions

External clock

input pulse

width low level

EXL

—

Figure 17.6

External clock

input pulse

width high level

EXH

—

External clock

rise time

EXr

—

7.5

—

5ns

External clock

fall time

EXf

—

7.5

—

5ns

0.4

0.6

0.4

0.6

0.4

0.6

cyc

φ ≥ 5 MHz

Clock pulse

width low level

—

φ < 5 MHz

Figure

19.4

0.4

0.6

0.4

0.6

0.4

0.6

cyc

φ ≥ 5 MHz

Clock pulse

width high level

—

φ < 5 MHz

Note:

Does not apply to the HD6472246.

Table 17.5 and figure 17.6 show the external clock input conditions when the duty adjustment

circuit is not used. When the duty adjustment circuit is not used, the

φ output waveform depends

on the external clock input waveform, and therefore no specifications are provided.

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