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H8S2245 Datasheet(PDF) 592 Page - Renesas Technology Corp |
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H8S2245 Datasheet(HTML) 592 Page - Renesas Technology Corp |
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592 / 818 page  Section 17 Clock Pulse Generator Rev.3.00 Mar. 26, 2007 Page 550 of 772 REJ09B0355-0300 Table 17.5 External Clock Input Conditions when Duty Adjustment Circuit Is Not Used V CC = 2.7 V to 5.5 V V CC = 2.7 V to 5.5 V* V CC = 5.0 V ±10% Item Symbol Min Max Min Max Min Max Unit Test Conditions External clock input pulse width low level t EXL 50 — 37.5 — 25 — ns Figure 17.6 External clock input pulse width high level t EXH 50 — 37.5 — 25 — ns External clock rise time t EXr — 10 — 7.5 — 5ns External clock fall time t EXf — 10 — 7.5 — 5ns Notes: When the duty adjustment circuit is not used, the maximum operating frequency falls according to the input waveform. (Example: When t EXL = tEXH = 25 ns and tEXr = tEXf = 5 ns, the clock cycle time = 60 ns, and therefore the maximum operating frequency = 16.7 MHz.) * Does not apply to the HD6472246. tEXH tEXL tEXr tEXf VCC × 0.5 EXTAL Figure 17.6 External Clock Input Timing |
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