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H8S2245 Datasheet(PDF) 606 Page - Renesas Technology Corp

Part # H8S2245
Description  Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
PDF  818 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S2245 Datasheet(HTML) 606 Page - Renesas Technology Corp

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Section 18 Power-Down Modes
Rev.3.00 Mar. 26, 2007 Page 564 of 772
REJ09B0355-0300
18.6
Software Standby Mode
18.6.1
Software Standby Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby
mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop.
However, the contents of the CPU's internal registers, RAM data, and the states of on-chip
supporting modules other than the SCI and A/D, and I/O ports, are retained. Whether the address
bus and bus control signals are placed in the high-impedance state or retain the output state can be
specified by the OPE bit in SBYCR.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
18.6.2
Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pins
IRQ0 to IRQ2), or by
means of the
RES pin or STBY pin.
Clearing with an Interrupt
When an NMI or IRQ0 to IRQ2 interrupt request signal is input, clock oscillation starts, and after
the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to the entire
H8S/2245 Group chip, software standby mode is cleared, and interrupt exception handling is
started.
When clearing software standby mode with an IRQ0 to IRQ2 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ2 is
generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU
side or has been designated as a DTC activation source.
Clearing with the
RES
RES
RES
RES Pin
When the
RES pin is driven low, clock oscillation is started. At the same time as clock oscillation
starts, clocks are supplied to the entire H8S/2245 Group chip. Note that the
RES pin must be held
low until clock oscillation stabilizes. When the
RES pin goes high, the CPU begins reset exception
handling.
Clearing with the
STBY
STBY
STBY
STBY Pin
When the
STBY pin is driven low, a transition is made to hardware standby mode.



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