H8S2245 datasheet(622/818 Pages) RENESAS

622 / 818 page

Section 19 Electrical Characteristics

Rev.3.00 Mar. 26, 2007 Page 580 of 772

REJ09B0355-0300

19.4.1

Clock Timing

Table 19.5 lists the clock timing

Table 19.5

Clock Timing

Condition A: V

CC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC,

SS = AVSS = 0 V, φ = 32 kHz to 10 MHz, Ta = –20 to +75°C (regular

specifications), T

a = –40 to +85°C (wide-range specifications)

Condition B: V

CC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC,

SS = AVSS = 0 V, φ = 32 kHz to 13 MHz, Ta = –20 to +75°C (regular

specifications), T

a = –40 to +85°C (wide-range specifications)

Condition C: V

CC = 5.0 V ±10%, AVCC = 5.0 V ±10%, Vref = 4.5 V to AVCC,

SS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications),

a = –40 to +85°C (wide-range specifications)

Condition A

Condition B

Condition C

Item

Symbol

Min

Max

Min

Max

Min

Max

Unit

Test

Conditions

Clock cycle time

cyc

100

31250

500

Figure 19.4

Clock high pulse

width

—

Clock low pulse

width

—

Clock rise time

—

5ns

Clock fall time

—

5ns

Clock oscillator

setting time at

reset (crystal)

OSC1

—

Figure 19.5

Clock oscillator

setting time in

software standby

(crystal)

OSC2

—

Figure 18.2

External clock

output stabilization

delay time

DEXT

500

—

500

—

500

—

µs

Figure 19.5

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