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H8S2245 Datasheet(PDF) 626 Page - Renesas Technology Corp |
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H8S2245 Datasheet(HTML) 626 Page - Renesas Technology Corp |
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626 / 818 page  Section 19 Electrical Characteristics Rev.3.00 Mar. 26, 2007 Page 584 of 772 REJ09B0355-0300 19.4.3 Bus Timing Table 19.7 lists the bus timing. Table 19.7 Bus Timing Condition A: V CC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, V SS = AVSS = 0 V, φ = 32 kHz to 10 MHz, Ta = –20 to +75°C (regular specifications), T a = –40 to +85°C (wide-range specifications) Condition B: V CC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, V SS = AVSS = 0 V, φ = 32 kHz to 13 MHz, Ta = –20 to +75°C (regular specifications), T a = –40 to +85°C (wide-range specifications) Condition C: V CC = 5.0 V ±10%, AVCC = 5.0 V ±10%, Vref = 4.5 V to AVCC, V SS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), T a = –40 to +85°C (wide-range specifications) Condition A Condition B Condition C Item Symbol Min Max Min Max Min Max Unit Test Conditions Address delay time t AD — 40 — 35 — 20 ns Address setup time t AS 0.5 × t cyc –30 — 0.5 × t cyc –20 — 0.5 × t cyc –15 — ns Figure 19.8 to Figure 19.12 Address hold time t AH 0.5 × t cyc –20 — 0.5 × t cyc –15 — 0.5 × t cyc –10 — ns CS delay time t CSD — 40 — 35 — 20 ns AS delay time t ASD — 60 — 50 — 30 ns RD delay time 1 t RSD1 — 60 — 45 — 30 ns RD delay time 2 t RSD2 — 60 — 45 — 30 ns Read data setup time t RDS 30 — 30 — 15 — ns Read data hold time t RDH 0 — 0 — 0 — ns Read data access time 1 t ACC1 — 1.0 × t cyc –50 — 1.0 × t cyc –55 — 1.0 × t cyc –25 ns Read data access time 2 t ACC2 — 1.5 × t cyc –50 — 1.5 × t cyc –55 — 1.5 × t cyc –25 ns Read data access time 3 t ACC3 — 2.0 × t cyc –50 — 2.0 × t cyc –55 — 2.0 × t cyc –25 ns Read data access time 4 t ACC4 — 2.5 × t cyc –50 — 2.5 × t cyc –55 — 2.5 × t cyc –25 ns |
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