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H8S2245 Datasheet(PDF) 697 Page - Renesas Technology Corp |
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H8S2245 Datasheet(HTML) 697 Page - Renesas Technology Corp |
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697 / 818 page ![]() Appendix B Register Field Rev.3.00 Mar. 26, 2007 Page 655 of 772 REJ09B0355-0300 BCRL—Bus Control Register L H'FED5 Bus Controller 7 BRLE 0 R/W 6 BREQOE 0 R/W 5 EAE 1 R/W 4 — 1 R/W 3 — 1 R/W 0 WAITE 0 R/W 2 ASS 1 R/W 1 — 0 R/W Bit Initial value Read/Write : : : Bus Release Enable 0 1 External bus release is disabled External bus release is enabled BREQO Pin Enable 0 1 BREQO output disabled BREQO output enabled External Addresses H'010000 to H'01FFFF Enable 0 1 Area Partition Unit Select 0 1 Area partition unit is 128 kbytes (1 Mbit) Area partition unit is 2 Mbytes (16 Mbits) WAIT Pin Enable 0 1 Wait input by WAIT pin disabled Note: * Do not access a reserved area. Wait input by WAIT pin enabled On-chip ROM (H8S/2246 and H8S/2245) or a reserved area (H8S/2244, H8S/2243, H8S/2242, and H8S/2241) External addresses (in external expansion mode) or reserved area* (in single-chip mode) |
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