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H8S2245 Datasheet(PDF) 704 Page - Renesas Technology Corp |
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H8S2245 Datasheet(HTML) 704 Page - Renesas Technology Corp |
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704 / 818 page  Appendix B Register Field Rev.3.00 Mar. 26, 2007 Page 662 of 772 REJ09B0355-0300 SCKCR—System Clock Control Register H'FF3A Clock Pulse Generator 7 PSTOP 0 R/W 6 — 0 R/W 5 — 0 — 4 — 0 — 3 — 0 — 0 SCK0 0 R/W 2 SCK2 0 R/W 1 SCK1 0 R/W 0 1 PSTOP Normal Operation φ output Fixed high High impedance High impedance Fixed high Fixed high φ Clock Output Control Bus Master Clock Select 0 1 0 1 0 1 0 1 0 1 0 1 — Bus master is in high-speed mode Medium-speed clock is φ/2 Medium-speed clock is φ/4 Medium-speed clock is φ/8 Medium-speed clock is φ/16 Medium-speed clock is φ/32 — φ output Fixed high Sleep Mode Bit Initial value Read/Write : : : Software Standby Mode Hardware Standby Mode MDCR—Mode Control Register H'FF3B MCU 7 — 1 — 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 0 MDS0 —* R 2 MDS2 —* R 1 MDS1 —* R Current mode pin operating mode Bit Initial value Read/Write : : : Note: * Determined by pins MD2 to MD0 |
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