H8S2245 datasheet(747/818 Pages) RENESAS

747 / 818 page

Appendix B Register Field

Rev.3.00 Mar. 26, 2007 Page 705 of 772

REJ09B0355-0300

TCSR0—Timer Control/Status Register 0

H'FFB2

8-Bit Timer Channel 0

TCSR1—Timer Control/Status Register 1

H'FFB3

8-Bit Timer Channel 1

CMFB

R/(W)*1

CMFA

R/(W)*1

OVF

R/(W)*1

—

OS3

R/W

OS0

R/W

OS2

R/W

OS1

R/W

TCSR1

CMFB

R/(W)*1

CMFA

R/(W)*1

OVF

R/(W)*1

ADTE

R/W

OS3

R/W

OS0

R/W

OS2

R/W

OS1

R/W

TCSR0

Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags.

2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0.

Compare Match Flag B

Compare Match Flag A

[Clearing condition]

Cleared by reading OVF when OVF = 1, then writing 0 to OVF

Timer Overflow Flag

A/D converter start requests by compare match A are disabled

A/D converter start requests by compare match A are enabled

A/D Trigger Enable (TCSR0 only)

No change when compare match B occurs

0 is output when compare match B occurs

1 is output when compare match B occurs

Output Select

No change when compare match A

occurs

Output Select

Output is inverted when compare

match A occurs (toggle output)

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

[Setting condition]

Set when TCNT overflows (changes from H'FF to H'00)

[Clearing conditions]

• Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA

• When the DTC*2 is activated by a CMIA interrupt, while DISEL bit of MRB in DTC is 0.

[Setting condition]

Set when TCNT matches TCORA

[Clearing conditions]

• Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB

• When the DTC*2 is activated by a CMIB interrupt, while DISEL bit of MRB in DTC is 0.

[Setting condition]

Set when TCNT matches TCORB

Output is inverted when compare match B occurs

(toggle output)

1 is output when compare match A

occurs

0 is output when compare match A

occurs

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