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H8S2245 Datasheet(PDF) 751 Page - Renesas Technology Corp |
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H8S2245 Datasheet(HTML) 751 Page - Renesas Technology Corp |
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751 / 818 page ![]() Appendix B Register Field Rev.3.00 Mar. 26, 2007 Page 709 of 772 REJ09B0355-0300 RSTCSR—Reset Control/Status Register H'FFBE (W) H'FFBF (R) WDT 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 — 1 — 3 — 1 — 0 — 1 — 2 — 1 — 1 — 1 — 0 1 [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF Watchdog Timer Overflow Flag Notes: The method for writing to RSTCSR is different from that for general registers to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access. * Can only be written with 0 for flag clearing. 0 1 Reset Enable Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows 0 1 Reset Select Power-on reset Manual reset Bit Initial value Read/Write : : : [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation Note: * The modules H8S/2245 Group are not reset, but TCNT and TCSR in WDT are reset. |
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