H8S2245 datasheet(290/818 Pages) RENESAS

290 / 818 page

Section 8 I/O Ports

Rev.3.00 Mar. 26, 2007 Page 248 of 772

REJ09B0355-0300

8.8.2

Table 8.13 shows the port B register configuration.

Table 8.13

Port B Registers

Name

Abbreviation

R/W

Initial Value

Address*

Port B data direction register

PBDDR

H'00

H'FEBA

Port B data register

PBDR

R/W

H'00

H'FF6A

Port B register

PORTB

Undefined

H'FF5A

Port B MOS pull-up control register

PBPCR

R/W

H'00

H'FF71

Note:

Lower 16 bits of the address.

Port B Data Direction Register (PBDDR)

PB7DDR

PB6DDR

PB5DDR

PB4DDR

PB3DDR

PB0DDR

PB2DDR

PB1DDR

Bit

Initial value

R/W

PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.

This register is a write-only register, and cannot be written by bit manipulation instruction. For

details, see section 2.10.4, Access Methods for Registers with Write-Only Bits.

PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its

prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to

select whether the address output pins retain their output state or become high-impedance when a

transition is made to software standby mode.

• Modes 1, 4, and 5

The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits.

• Modes 2 and 6

Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while

clearing the bit to 0 makes the pin an input port.

Note:

Modes 2 and 6 cannot be used in the H8S/2240.

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