H8S2245 datasheet(291/818 Pages) RENESAS

291 / 818 page

Section 8 I/O Ports

Rev.3.00 Mar. 26, 2007 Page 249 of 772

REJ09B0355-0300

• Modes 3 and 7

Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing

the bit to 0 makes the pin an input port.

Note:

Modes 3 and 7 cannot be used in the H8S/2240.

Port B Data Register (PBDR)

PB7DR

R/W

PB6DR

R/W

PB5DR

R/W

PB4DR

R/W

PB3DR

R/W

PB0DR

R/W

PB2DR

R/W

PB1DR

R/W

Bit

Initial value

R/W

PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB

7 to PB0).

PBDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior

state after a manual reset, and in software standby mode.

Port B Register (PORTB)

PB7

—*

PB6

—*

PB5

—*

PB4

—*

PB3

—*

PB0

—*

PB2

—*

PB1

—*

Bit

Initial value

R/W

Note: * Determined by state of pins PB7 to PB0.

PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port B pins (PB

7 to PB0) must always be performed on PBDR.

If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B

read is performed while PBDDR bits are cleared to 0, the pin states are read.

After a power-on reset and in hardware standby mode, PORTB contents are determined by the pin

states, as PBDDR and PBDR are initialized. PORTB retains its prior state after a manual reset, and

in software standby mode.

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