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H8S2245 Datasheet(PDF) 303 Page - Renesas Technology Corp |
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H8S2245 Datasheet(HTML) 303 Page - Renesas Technology Corp |
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303 / 818 page ![]() Section 8 I/O Ports Rev.3.00 Mar. 26, 2007 Page 261 of 772 REJ09B0355-0300 Port D Data Register (PDDR) 7 PD7DR 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 0 PD0DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W Bit Initial value R/W : : : PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD 7 to PD0). PDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port D Register (PORTD) 7 PD7 —* R 6 PD6 —* R 5 PD5 —* R 4 PD4 —* R 3 PD3 —* R 0 PD0 —* R 2 PD2 —* R 1 PD1 —* R Bit Initial value R/W Note: * Determined by state of pins PD7 to PD0. : : : PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port D pins (PD 7 to PD0) must always be performed on PDDR. If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTD contents are determined by the pin states, as PDDDR and PDDR are initialized. PORTD retains its prior state after a manual reset, and in software standby mode. |
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