H8S2245 datasheet(316/818 Pages) RENESAS

316 / 818 page

Section 8 I/O Ports

Rev.3.00 Mar. 26, 2007 Page 274 of 772

REJ09B0355-0300

After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin

states, as PFDDR and PFDR are initialized. PORTF retains its prior state after a manual reset, and

in software standby mode.

8.12.3

Pin Functions

Port F pins also function as bus control signal input/output pins (

AS, RD, HWR, LWR, WAIT,

BREQO, BREQ, and BACK), the system clock (φ) output pin and interrupt input pins (IRQ0 to

IRQ 3). The pin functions differ between modes 1, 2, 4, 5, and 6, and modes 3 and 7. Port F pin

functions are shown in table 8.22.

Table 8.22

Port F Pin Functions

Selection Method and Pin Functions

7/φ

The pin function is switched as shown below according to bit PF7DDR.

PF7DDR

Pin function

7 input pin

φ output pin

6/AS

The pin function is switched as shown below according to the operating mode

and bit PF6DDR.

Operating

Mode

Modes 1, 2, 4, 5, 6*

Modes 3 and 7*

PF6DDR

—

Pin function

AS output pin

6 input pin

6 output pin

Note:

Modes 2, 3, 6, and 7 cannot be used in the H8S/2240.

5/RD

The pin function is switched as shown below according to the operating mode

and bit PF5DDR.

Operating

Mode

Modes 1, 2, 4, 5, 6*

Modes 3 and 7*

PF5DDR

—

Pin function

RD output pin

5 input pin

5 output pin

Note:

Modes 2, 3, 6, and 7 cannot be used in the H8S/2240.

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