H8S2245 datasheet(320/818 Pages) RENESAS

320 / 818 page

Section 8 I/O Ports

Rev.3.00 Mar. 26, 2007 Page 278 of 772

REJ09B0355-0300

8.13.2

Table 8.23 shows the port G register configuration.

Table 8.23

Port G Registers

Name

Abbreviation

R/W

Initial Value*

Address*

Port G data direction register

PGDDR

H'00/H'10*

H'FEBF

Port G data register

PGDR

R/W

H'00

H'FF6F

Port G register

PORTG

Undefined

H'FF5F

Notes: 1. Value of bits 4 to 0.

2. Lower 16 bits of the address.

3. Initial value depends on the mode.

Port G Data Direction Register (PGDDR)

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

PG4DDR

PG3DDR

PG0DDR

PG2DDR

PG1DDR

Bit

Modes 1, 4, 5

Initial value

R/W

Modes 2, 3, 6, 7

Initial value

R/W

PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an

undefined value will be read. PGDDR cannot be modified.

This register is a write-only register, and cannot be written by bit manipulation instruction. For

details, see section 2.10.4, Access Methods for Registers with Write-Only Bits.

PGDDR is initialized by a power-on reset, and in hardware standby mode, to H'10 (bits 4 to 0) in

modes 1, 4, and 5, and to H'00 (bits 4 to 0) in modes 2, 3, 6, and 7. It retains its prior state after a

manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the

bus control output pins retain their output state or become high-impedance when a transition is

made to software standby mode.

Note:

Modes 2, 3, 6, and 7 cannot be used in the H8S/2240.

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