H8S2245 datasheet(321/818 Pages) RENESAS

321 / 818 page

Section 8 I/O Ports

Rev.3.00 Mar. 26, 2007 Page 279 of 772

REJ09B0355-0300

• Modes 1, 2, 4, 5, and 6

Pins PG

4 to PG1 function as bus control output pins (CS0 to CS3) when the corresponding

PGDDR bits are set to 1, and as input ports when the bits are cleared to 0.

Pin PG

0 is an output port when the corresponding PGDDR bit is set to 1, and an input port

when the bit is cleared to 0.

Note:

Modes 2 and 6 cannot be used in the H8S/2240.

• Modes 3 and 7

Setting a PGDDR bit to 1 makes the corresponding port G pin an output port, while clearing

the bit to 0 makes the pin an input port.

Note:

Modes 3 and 7 cannot be used in the H8S/2240.

Port G Data Register (PGDR)

—

Undefined

—

Undefined

—

Undefined

—

PG4DR

R/W

PG3DR

R/W

PG0DR

R/W

PG2DR

R/W

PG1DR

R/W

Bit

Initial value

R/W

PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG

4 to PG0).

Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.

PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. It

retains its prior state after a manual reset, and in software standby mode.

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